1 hgtd8p50g1, hgtd8p50g1s 8a, 500v p-channel igbts package jedec to-251aa jedec to-252aa symbol (flange) collector emitter collector gate (flange) collector gate emitter c g e features ? 8a, 500v ? 3.7v v ce(sat) ? typical fall time - 1800ns ? high input impedance ?t j = +150 o c description the hgtd8p50g1 and the hgtd8p50g1s are p-channel enhancement-mode insulated gate bipolar transistors (igbts) designed for high voltage, low on-dissipation applications such as switching regulators and motor drives. this p- channel igbt can be paired with n-channel igbts to form a complementary power switch and it is ideal for half bridge circuit con?gurations. these types can be operated directly from low power integrated circuits. the development type number for these devices is ta49015. packaging availability part number package brand hgtd8p50g1 to-251aa g8p50g hgtd8p50g1s to-252aa g8p50g note: when ordering, use the entire part number. add the suf?x 9a to obtain the to-252aa variant in the tape and reel, i.e., hgtd8p50g1s9a. march 1997 absolute maximum ratings t c = +25 o c, unless otherwise speci?ed hgtd8p50g1/g1s units collector-emitter breakdown voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bv ces -500 v emitter-collector breakdown voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bv ecs 10 v collector current continuous at t c = +25 o c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i c25 at t c = +90 o c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i c90 -12 -8 a a collector current pulsed (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i cm -18 a gate-emitter voltage continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ges 20 v gate-emitter voltage pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gem 30 v switching soa at t c = +25 o c, v cl = -350v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ssoa no snubber, figure 17 - circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . with 0.1 m f capacitor, figure 17 - circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3 -18 a a power dissipation total at t c = +25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d 66 w power dissipation derating t c > +25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.53 w/ o c operating and storage junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -40 to +150 o c maximum lead temperature for soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l (0.125" from case for 5s) +260 o c note: 1. t j = 25 o c, v cl = 350v, r ge = 25 w, figure 17 - circuit 2 (c 1 = 0.1 m f) file number 3649.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
2 speci?cations hgtd8p50g1, hgtd8p50g1s electrical speci?cations t c = +25 o c, unless otherwise speci?ed parameters symbol test conditions min typ max unit collector-emitter breakdown voltage bv ces i ce = -250 m a v cl = -600v v ge = 0v -500 - - v emitter-collector breakdown voltage bv ecs i ec = 1ma v ge = 0v 10 - - v collector-emitter leakage current i ces v ce = bv ces t c = +25 o c - - -250 m a v ce = 0.8 bv ces t c = +150 o c - - -1.0 ma collector-emitter saturation voltage v ce(sat) i ce = -3.0a v ge = -15v t c = +25 o c - -2.5 -2.9 v t c = +150 o c - -2.3 -2.8 v i ce = i c90 v ge = -15v t c = +25 o c - -3.0 -3.7 v t c = +150 o c - -3.3 -4.0 v gate-emitter threshold voltage v ge(th) i ce = -1.0ma v ce = v ge -4.5 -6.0 -7.5 v gate-emitter leakage current i ges v ge = 20v - - 100 na gate-emitter plateau voltage v ge(pl) i c = 3a v ce = 0.5 bv ces - -7.0 - v on-state gate charge q g(on) i c = 3a, v ce = 0.5 bv ces v ge = -15v - 16 25 nc v ge = -20v - 22 30 nc current turn-on delay time t d(on)i r l = 113 w i ce = -3a, v ge = -15v v ce = -350v r g = 25 w t j = +150 o c fig. 17, circuit 1 -45-ns current rise time t ri -85-ns current turn-off delay time t d(off)i l = 100 m h - 480 680 ns current fall time t fi - 1800 2500 ns turn-off energy (note 1) e off - 0.8 - mj current turn-off delay time t d(off)i l = 100 m hi ce = -8a, v ge = -15v v ce = -350v r g = 25 w t j = +150 o c fig. 17, circuit 2 c 1 = .022 m f - 100 200 ns current fall time t fi - 3500 4000 ns turn-off energy (note 1) e off - 1.3 - mj latching current i l l = 100 m hv ge = -15v r g = 25 w t j = +25 o c v ce = -350v fig. 17, circuit 1 -3 - - a thermal resistance r q jc - 1.75 1.90 o c/w note: 1. turn-off energy loss (e off ) is de?ned as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the collector current equals zero (i ce = 0a). the hgtd8p50g1 and hgtd8p50g1s were tested per jedec standard no. 24-1 method for measurement of power device turn-off switching loss. this test method produces the true total turn -off energy loss. turn-on losses include diode losses.
3 hgtd8p50g1, hgtd8p50g1s typical performance curves figure 1. transfer characteristics figure 2. saturation characteristics figure 3. maximum dc collector current as a function of case temperature figure 4. collector-emitter saturation voltage figure 5. capacitance as a function of collector- emitter voltage figure 6. normalized switching waveforms at constant gate current. (refer to application notes an7254 and an7260) pulse duration = 250 m s, duty cycle < 0.5%, v ce = -10v 0 -4 -8 -12 -16 -20 i ce , collector-emitter current (a) -4 -6 -8 -10 -12 v ge , gate-to-emitter voltage (v) t c = +150 o c t c = -40 o c -14 t c = +25 o c pulse duration = 250 m s, duty cycle < 0.5% -6.5v -7.0v -9.0v -2 -4 -6 -8 -10 0 -20 -16 -12 -8 -4 0 v ce , collector-emitter voltage (v) i ce , collector-emitter current (a) -8.0v v ge = -15v -12v -10v 25 50 75 100 125 150 -2 -4 -6 -8 -10 -12 -14 0 i ce , dc collector current (a) t c , case temperature ( o c) v ge = -15v i ce , collector-emitter current (a) -4 0 -8 -12 -16 -20 0-1 -2 -3 -4 -5 -6 -7 v ce , collector-emitter voltage (v) pulse duration = 250 m s, duty cycle < 0.5%, v ge = -15v t c = +150 o c t c = +25 o c t c = -40 o c frequency = 1mhz c ies c oes c res 0 -5 -10 -15 -20 -25 0 100 200 300 400 500 600 700 c, capacitance (pf) v ce , collector-emitter voltage (v) 0 -7.5 -15 v ge , gate-emitter voltage (v) v ce, collector-emitter voltage (v) 0 -200 -400 gate-emitter voltage collector-emitter voltage t j = +25 o c, v ge = -15v, i g(ref) = -0.391ma v ce = -100v v ce = -400v v ce = -400v 20 i g(ref) i g(act) 80 i g(ref) i g(act) time ( m s)
4 hgtd8p50g1, hgtd8p50g1s figure 7. saturation voltage as a function of collector-emitter current figure 8. turn-off switching loss as a function of collector-emitter current figure 9. turn-off delay as a function of collector- emitter current figure 10. operating frequency as a function of collector-emitter current and voltage figure 11. fall time as a function of collector- emitter current figure 12. latching current as a function of snubber capacitance typical performance curves (continued) t j = +150 o c v ce(sat) , saturation voltage (v) -1 -5 -10 i ce , collector-emitter current (a) 0 -2 -4 -6 -8 -10 -12 -14 v ge = -10v v ge = -15v t j = +150 o c, r g = 25 w, l = 100 m h 0.1 1.0 10 w off , turn-off switching loss (mj) -1 -2 -3 -4 -5 i ce , peak collector-emitter current (a) v ce = -350v, v ge = -15v v ce = -200v, v ge = -15v fig. 17, circuit 1 r ge = 50 w r ge = 25 w t j = +150 o c, v ce = -350v, v ge = -15v, l = 100 m h fig. 17, circuit 1 0.1 0.5 1.0 t d(off)i , turn-off delay time ( m s) -1 -2 -3 -4 -5 i ce , peak collector-emitter current (a) f max2 = (p d - p c )/e off f max1 = 0.05/ t d(off)i p d = allowable dissipation p c = conduction dissipation (duty factor = 50%) r q jc = 1.9 o c/w t j = +150 o c, t c = +75 o c, v ge = -15v, r ge = 25 w , l = 100 m h f max , operating frequency (khz) 10 100 50 -1 -5 -10 i ce , peak collector-emitter current (a) fig. 17, circuit 1 v ce = -350v v ce = -200v v ce = -350v fig. 17, circuit 1 t j = +150 o c, v ge = -15v, r g = 25 w , l = 100 m h 1 2 3 4 5 t fi , fall time ( m s) -1 -3 -4 -5 -2 i ce , collector-emitter current (a) fig. 17, circuit 2 v ce = -350v t j = 25 o c, v ge = -15v, r g = 25 w , l = 100 m h i ce , peak collector-emitter current (a) 0 -10 -15 -20 -25 -5 c1, snubber capacitance ( m f) 10 0 10 -1 10 -2 10 -3 10 -4 10 -5
5 hgtd8p50g1, hgtd8p50g1s figure 13. latching current as a function of junction temperature figure 14. gate threshold voltage as a function of junction temperature figure 15. igbt normalized transient thermal impedance, junction to case figure 16. latching current as a function of collector-emitter voltage test circuits figure 17. inductive switching test circuits typical performance curves (continued) fig. 17, circuit 1 v ce = -350v, v ge = -15v, r g = 25 w , l = 100 m h i ce , peak collector-emitter -3 -4 -5 -6 -7 -50 0 50 100 150 t c , case temperature ( o c) current (a) -40 0 40 80 120 160 v th , gate threshold voltage (v) 4.5 5.5 6.0 6.5 5.0 t c , case temperature ( o c) v ce = v ge , i ce = 1.0ma t 1 , rectangular pulse duration (s) z q jc , normalized thermal response ( o c/w) single pulse 0.5 0.2 0.1 0.05 0.02 0.01 p ds t 1 t 2 notes: 1. duty factor, d = t 1 / t 2 2.peak t j = (p ds x z q jc x r q jc ) + t a 10 1 10 0 10 -1 10 -2 10 -3 10 -4 10 -5 10 0 10 -1 10 -3 10 -2 0 200 100 300 400 500 0 3 6 9 12 15 i ce , peak collector-emitter v ce , collector-emitter (v) t c = 25 o c, v ge = -15v, r g = 25 w , l = 100 m h fig. 17, circuit 1 current (a) r g = 25 w l = 100 m h + - v cc = 350v circuit 1 r g = 25 w l = 100 m h + - c 1 v cc = 350v d 1 d 1 = gsi t ran z orb circuit 2
6 hgtd8p50g1, hgtd8p50g1s operating frequency information operating frequency information for a typical device (figure 10) is presented as a guide for estimating device performance for a speci?c application. other typical frequency vs collector current (i ce ) plots are possible using the information shown for a typical unit in figure 7, figure 8 and figure 9. the oper- ating frequency plot (figure 10) of a typical device shows f max1 or f max2 whichever is smaller at each point. the infor- mation is based on measurements of a typical device and is bounded by the maximum rated junction temperature. f max1 is de?ned by f max1 = 0.05/t d(off)i . t d(off)i deadtime (the denominator) has been arbitrarily held to 10% of the on- state time for a 50% duty factor. other de?nitions are possible. t d(off)i is de?ned as the time between the 90% point of the trailing edge of the input pulse and the point where the collector current falls to 90% of its maximum value. device turn-off delay can establish an additional fre- quency limiting condition for an application other than t jmax . t d(off)i is important when controlling output ripple under a lightly loaded condition. f max2 is de?ned by f max2 = (p d - p c )/e off . the allowable dissipation (p d ) is de?ned by p d = (t jmax - t c )/r q jc . the sum of device switching and conduc- tion losses must not exceed pd. a 50% duty factor was used (figure 10) and the conduction losses (pc) are approximated by pc = (v ce i ce )/2. e off is de?ned as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the collector current equals zero (i ce = 0a). the switching power loss (figure 10) is de?ned as f max2 e off . turn-on switching losses are not included because they can be greatly in?uenced by external circuit conditions and components. handling precautions for igbts insulated gate bipolar transistors are susceptible to gate- insulation damage by the electrostatic discharge of energy through the devices. when handling these devices, care should be exercised to assure that the static charge built in the handlers body capacitance is not discharged through the device. with proper handling and application procedures, however, igbts are currently being extensively used in production by numerous equipment manufacturers in military, industrial and consumer applications, with virtually no damage problems due to electrostatic discharge. igbts can be handled safely if the following basic precautions are taken: 1. prior to assembly into a circuit, all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conductive material such as ? eccosorbd ld26 or equivalent. 2. when devices are removed by hand from their carriers, the hand being used should be grounded by any suitable means - for example, with a metallic wristband. 3. tips of soldering irons should be grounded. 4. devices should never be inserted into or removed from circuits with power on. 5. gate voltage rating - never exceed the gate-voltage rating of v gem . exceeding the rated v ge can result in per- manent damage to the oxide layer in the gate region. 6. gate termination - the gates of these devices are essentially capacitors. circuits that leave the gate open- circuited or ?oating should be avoided. these conditions can result in turn-on of the device due to voltage buildup on the input capacitor due to leakage currents or pickup. 7. gate protection - these devices do not have an internal monolithic zener diode from gate to emitter. if gate protection is required an external zener is recommended. ? trademark emerson and cumming, inc. intersilt corporation product is covered by one or more of the following u.s. patents: 4,364,073 4,417,385 4,430,792 4,443,931 4,466,176 4,516,143 4,532,534 4,567,641 4,587,713 4,598,461 4,605,948 4,618,872 4,620,211 4,631,564 4,639,754 4,639,762 4,641,162 4,644,637 4,682,195 4,684,413 4,694,313 4,717,679 4,743,952 4,783,690 4,794,432 4,801,986 4,803,533 4,809,045 4,809,047 4,810,665 4,823,176 4,837,606 4,860,080 4,883,767 4,888,627 4,890,143 4,901,127 4,904,609 4,933,740 4,963,951 4,969,027
7 hgtd8p50g1, hgtd8p50g1s to-251aa 3 lead jedec to-251aa plastic package lead 1 gate lead 2 collector lead 3 emitter term. 4 collector b 2 e a c seating l 1 d l b e 123 b 1 h 1 j 1 a 1 e 1 term. 4 plane symbol inches millimeters notes min max min max a 0.086 0.094 2.19 2.38 - a 1 0.018 0.022 0.46 0.55 3, 4 b 0.028 0.032 0.72 0.81 3, 4 b 1 0.033 0.040 0.84 1.01 3 b 2 0.205 0.215 5.21 5.46 3, 4 c 0.018 0.022 0.46 0.55 3, 4 d 0.270 0.290 6.86 7.36 - e 0.250 0.265 6.35 6.73 - e 0.090 typ 2.28 typ 5 e 1 0.180 bsc 4.57 bsc 5 h 1 0.035 0.045 0.89 1.14 - j 1 0.040 0.045 1.02 1.14 6 l 0.355 0.375 9.02 9.52 - l 1 0.075 0.090 1.91 2.28 2 notes: 1. these dimensions are within allowable dimensions of rev. c of jedec to-251aa outline dated 9-88. 2. solder finish uncontrolled in this area. 3. dimension (without solder). 4. add typically 0.002 inches (0.05mm) for solder plating. 5. position of lead to be measured 0.250 inches (6.35mm) from bot- tom of dimension d. 6. position of lead to be measured 0.100 inches (2.54mm) from bot- tom of dimension d. 7. controlling dimension: inch. 8. revision 2 dated 10-95.
8 hgtd8p50g1, hgtd8p50g1s to-252aa surface mount jedec to-252aa plastic package lead 1 gate lead 3 source term. 4 collector b 2 e d l 3 l e b 1 b 13 a l c seating back view 2 h 1 a 1 b 3 e 1 j 1 l 1 term. 4 0.265 minimum pad size recommended for surface-mounted applications (6.7) 0.265 (6.7) 0.070 (1.8) 0.118 (3.0) 0.063 (1.6) 0.090 (2.3) 0.063 (1.6) 0.090 (2.3) plane symbol inches millimeters notes min max min max a 0.086 0.094 2.19 2.38 - a 1 0.018 0.022 0.46 0.55 4, 5 b 0.028 0.032 0.72 0.81 4, 5 b 1 0.033 0.040 0.84 1.01 4 b 2 0.205 0.215 5.21 5.46 4, 5 b 3 0.190 - 4.83 - 2 c 0.018 0.022 0.46 0.55 4, 5 d 0.270 0.290 6.86 7.36 - e 0.250 0.265 6.35 6.73 - e 0.090 typ 2.28 typ 7 e 1 0.180 bsc 4.57 bsc 7 h 1 0.035 0.045 0.89 1.14 - j 1 0.040 0.045 1.02 1.14 - l 0.100 0.115 2.54 2.92 - l 1 0.020 - 0.51 - 4, 6 l 2 0.025 0.040 0.64 1.01 3 l 3 0.170 - 4.32 - 2 notes: 1. these dimensions are within allowable dimensions of rev. b of jedec to-252aa outline dated 9-88. 2. l 3 and b 3 dimensions establish a minimum mounting surface for terminal 4. 3. solder finish uncontrolled in this area. 4. dimension (without solder). 5. add typically 0.002 inches (0.05mm) for solder plating. 6. l 1 is the terminal length for soldering. 7. position of lead to be measured 0.090 inches (2.28mm) from bottom of dimension d. 8. controlling dimension: inch. 9. revision 5 dated 10-95.
9 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hgtd8p50g1, hgtd8p50g1s to-252aa 16mm tape and reel 330mm 50mm 13mm 22.4mm 16.4mm 2.0mm 4.0mm 1.75mm 1.5mm dia. hole c l cover tape user direction of feed 8.0mm 16mm general information 1. use "9a" suffix on part number. 2. 2500 pieces per reel. 3. order in multiples of full reels only. 4. meets eia-481 revision "a" specifications. revision 5 dated 10-95
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